#!/usr/bin/env python
# coding: utf-8

# # Direct translation to RTL

# In[1]:


from myirl.emulation.myhdl import *


# In[2]:


@block
def unitx(clk, a, b):
    @always(clk.posedge)
    def worker():
        if a < 20:
            b.next = concat(a[3:], a[4:])
            if a > 6:
                b.next = 0
        elif a < 4:
            b.next = 44
        
    return instances()


# In[3]:


from myirl.targets import pyosys

def test():
    
    clk = ClkSignal()
    a, b = [ Signal(intbv()[7:]) for _ in range(2) ]
    u = unitx(clk, a, b)

    r = pyosys.RTLIL("top1")
    d = u.elab(r)
    d[0].run("opt")
    d[0].display_rtl(fmt="dot")
    return d[0]
design = test()


# In[4]:


from yosys import display
display.display_dot(design.name)