val path = System.getProperty("user.dir") + "/source/load-ivy.sc"
interp.load.module(ammonite.ops.Path(java.nio.file.FileSystems.getDefault().getPath(path)))

import chisel3._
import chisel3.util._
import chisel3.tester._
import chisel3.tester.RawTester.test
import dotvisualizer._

class InstructionMemory(addr_width: Int, instr_width: Int, content: Seq[UInt]) extends Module {
  val io = IO(new Bundle {
    val address = Input(UInt(addr_width.W))
    val data_out = Output(UInt(instr_width.W))
  })
  val rom = VecInit(content)
    
  io.data_out := rom(io.address)
}

val instructions = Vector(33.U,1256.U,555.U)
test(new InstructionMemory(8,16,instructions)) { c =>
  for (i <- 0 until instructions.length) {
    c.io.address.poke(i.U)
    c.io.data_out.expect(instructions(i))
  }
}
println("SUCCESS!!")

class FetchUnit(addr_width: Int, instr_width: Int, content: Seq[UInt]) extends Module {
  val io = IO(new Bundle {
    val branch_pc = Input(UInt(addr_width.W))
    val pc_sel = Input(UInt(1.W))
    val next_pc = Output(UInt(addr_width.W))
    val instruction = Output(UInt(instr_width.W))
  })
  
  // instruction memory instance  
  val iMem = Module(new InstructionMemory(addr_width,instr_width,content))
  // pc register
  val pcReg = RegInit(0.U(addr_width.W))  
  // output of pc+1 adder
  val addr_plus_1 = pcReg + 1.U  
  
  // συμπληρώστε τις συνδέσεις των σημάτων σύμφωνα με το σχήμα
    
}

val instructions = Vector(33.U,1256.U,555.U)
test(new FetchUnit(8,16,instructions)) { c =>

  // test instruction output when incrementing pc  
  c.io.pc_sel.poke(0.U)
  for (i <- 0 until instructions.length) {
    c.io.instruction.expect(instructions(i))
    c.clock.step()  
  }
    
  // test instruction output with input branch pc  
  c.io.pc_sel.poke(1.U)
  c.io.branch_pc.poke(1.U)
  c.clock.step()
  c.io.instruction.expect(instructions(1))
}
println("SUCCESS!!")