This variant uses mixed myIRL and cythonized myhdl code segments. Note that the procedural generation is quite a bit faster.
We import the barrelshifter library:
from library.barrelshifter import *
Then we create a barrel shifter generator with data width 32 (power 5):
W_POWER = 5
TEST_VALUES = [
(0xdead, 8, 0xdead << 8),
(0x8f01, 15, 0x8f01 << 15),
]
b = BarrelShifterGenerator(W_POWER)
Then we instance it first time in the test bench below. Note the instancing time on this first run.
from myirl.test.common_test import gen_osc
from myirl.emulation.myhdl import *
@block
def top_bs(b):
clk = ClkSignal()
ce = Signal(bool())
val, result = [ Signal(intbv(0xaa00)[2 ** W_POWER:]) for i in range(2) ]
s = Signal(intbv()[W_POWER:])
inst = [
b.barrel_shifter(clk, ce, val, s, result, False),
gen_osc(clk, 2)
]
@instance
def stim():
for item in TEST_VALUES:
ce.next = False
s.next = item[1]
val.next = item[0]
yield(clk.posedge)
ce.next = True
yield(clk.posedge)
yield(clk.posedge)
print(result)
assert result == item[2]
raise StopSimulation
inst += [ stim ]
return inst
@utils.timer
def test(b):
return top_bs(b)
design = test(b)
DEBUG UNHANDLED CLASS <class 'ipykernel.zmqshell.ZMQInteractiveShell'> Declare obj 'barrel_shifter' in context '(LIB: BarrelShifterGenerator 'bs')' Declare obj 'shifter_stage' in context '(LIB: BarrelShifterGenerator 'bs')' Declare obj 'cshift' in context '(LIB: BarrelShifterGenerator 'bs')' Module bs: Existing instance cshift, rename to cshift_1 Module bs: Existing instance shifter_stage, rename to shifter_stage_1 Module bs: Existing instance shifter_stage, rename to shifter_stage_2 Module bs: Existing instance shifter_stage, rename to shifter_stage_3 Module bs: Existing instance shifter_stage, rename to shifter_stage_4 Finished test in 0.2787 secs
Running the test bench again, the duration is a little less than on the first run, because this module was already compiled.
design = test(b)
DEBUG UNHANDLED CLASS <class 'ipykernel.zmqshell.ZMQInteractiveShell'>
Module top_bs: Existing instance top_bs, rename to top_bs_1
Finished test in 0.0844 secs
Finally, the quick & dirty verification:
from myirl import targets
from myirl.test.common_test import run_ghdl
f = design.elab(targets.VHDL, elab_all = True)
f += b.elab(targets.VHDL)
# print(f)
run_ghdl(f, design, vcdfile = 'bs.vcd', debug = True)
Writing 'top_bs_1' to file /tmp/myirl_top_bs_hkuke_t6/top_bs_1.vhdl Creating library file /tmp/myirl_module_defs_8zz0e64r/module_defs.vhdl Writing 'shifter_stage_4' to file /tmp/myirl_bs_se_ljmom/shifter_stage_4.vhdl Writing 'shifter_stage_3' to file /tmp/myirl_bs_se_ljmom/shifter_stage_3.vhdl Writing 'shifter_stage_2' to file /tmp/myirl_bs_se_ljmom/shifter_stage_2.vhdl Writing 'shifter_stage_1' to file /tmp/myirl_bs_se_ljmom/shifter_stage_1.vhdl Writing 'cshift_1' to file /tmp/myirl_bs_se_ljmom/cshift_1.vhdl
../../myirl/kernel/components.py:183: UserWarning: @interface `shifter_stage_4`: Unspecified port I/O 'msb' => IN base.warnings.warn((msg + " => IN") % n) ../../myirl/kernel/components.py:183: UserWarning: @interface `shifter_stage_4`: Unspecified port I/O 'sbit' => IN base.warnings.warn((msg + " => IN") % n) ../../myirl/kernel/components.py:183: UserWarning: @interface `shifter_stage_3`: Unspecified port I/O 'msb' => IN base.warnings.warn((msg + " => IN") % n) ../../myirl/kernel/components.py:183: UserWarning: @interface `shifter_stage_3`: Unspecified port I/O 'sbit' => IN base.warnings.warn((msg + " => IN") % n) ../../myirl/kernel/components.py:183: UserWarning: @interface `shifter_stage_2`: Unspecified port I/O 'msb' => IN base.warnings.warn((msg + " => IN") % n) ../../myirl/kernel/components.py:183: UserWarning: @interface `shifter_stage_2`: Unspecified port I/O 'sbit' => IN base.warnings.warn((msg + " => IN") % n) ../../myirl/kernel/components.py:183: UserWarning: @interface `shifter_stage_1`: Unspecified port I/O 'msb' => IN base.warnings.warn((msg + " => IN") % n) ../../myirl/kernel/components.py:183: UserWarning: @interface `shifter_stage_1`: Unspecified port I/O 'sbit' => IN base.warnings.warn((msg + " => IN") % n) ../../myirl/kernel/components.py:183: UserWarning: @interface `shifter_stage`: Unspecified port I/O 'msb' => IN base.warnings.warn((msg + " => IN") % n) ../../myirl/kernel/components.py:183: UserWarning: @interface `shifter_stage`: Unspecified port I/O 'sbit' => IN base.warnings.warn((msg + " => IN") % n)
Writing 'cshift' to file /tmp/myirl_bs_se_ljmom/cshift.vhdl Writing 'shifter_stage' to file /tmp/myirl_bs_se_ljmom/shifter_stage.vhdl Writing 'barrel_shifter' to file /tmp/myirl_bs_se_ljmom/barrel_shifter.vhdl Creating library file /tmp/myirl_module_defs_xpdyoldv/module_defs.vhdl ==== COSIM stderr ==== /tmp/myirl_module_defs_xpdyoldv/module_defs.vhdl:6:1:warning: package "module_defs" was also defined in file "/tmp/myirl_module_defs_8zz0e64r/module_defs.vhdl" [-Wlibrary] ==== COSIM stdout ==== 0x00DEAD00 0x47808000 simulation stopped @22ns
0
# !cat -n /tmp/barrel_shifter.vhdl