Direct translation to RTL

In [1]:
from myirl.emulation.myhdl import *
In [2]:
@block
def unitx(clk, a, b):
    @always(clk.posedge)
    def worker():
        if a < 20:
            b.next = concat(a[3:], a[4:])
            if a > 6:
                b.next = 0
        elif a < 4:
            b.next = 44
        
    return instances()
In [3]:
from myirl.targets import pyosys

def test():
    
    clk = ClkSignal()
    a, b = [ Signal(intbv()[7:]) for _ in range(2) ]
    u = unitx(clk, a, b)

    r = pyosys.RTLIL("top1")
    d = u.elab(r)
    d[0].run("opt")
    d[0].display_rtl(fmt="dot")
    return d[0]
design = test()
 DEBUG CREATE wrapper module for unitx (EmulationModule 'top_unitx') 
Creating process 'unitx/worker' with sensitivity (clk'rising,)
 Adding module with name `unitx` 

-- Running command `opt' --

1. Executing OPT pass (performing simple optimizations).

1.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module unitx.

1.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\unitx'.
Removed a total of 0 cells.

1.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \unitx..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~1 debug messages>

1.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \unitx.
Performed a total of 0 changes.

1.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\unitx'.
Removed a total of 0 cells.

1.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $worker::b_af19 ($dff) from module unitx (D = $auto$yosys.pyosys_wrappers:0:$10, Q = $b_ff).

1.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \unitx..
Removed 0 unused cells and 7 unused wires.
<suppressed ~1 debug messages>

1.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module unitx.
<suppressed ~1 debug messages>

1.9. Rerunning OPT passes. (Maybe there is more to do..)

1.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \unitx..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~1 debug messages>

1.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \unitx.
Performed a total of 0 changes.

1.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\unitx'.
Removed a total of 0 cells.

1.13. Executing OPT_DFF pass (perform DFF optimizations).

1.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \unitx..

1.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module unitx.

1.16. Finished OPT passes. (There is nothing left to do.)

-- Running command `show -format dot -prefix top1 ' --

2. Generating Graphviz representation of design.
Writing dot description to `top1.dot'.
Dumping module unitx to page 1.
In [4]:
from yosys import display
display.display_dot(design.name)
Out[4]:
unitx unitx n8 a c20 A B $worker:10::4da5/gt:_u $gt Y n8:e->c20:w c21 A B $worker:8::4021/gt:_u $gt Y n8:e->c21:w c22 A B $worker:8::9558/gt:_u $gt Y n8:e->c22:w x4 2:0 - 6:4 3:0 - 3:0 n8:e->x4:w n8:e->x4:w n9 b n10 clk c15 CLK D EN $11 $dffe Q n10:e->c15:w c15:e->n9:w c18 A $13 $reduce_bool Y c18:e->c15:w x0 0:0 - 1:1 0:0 - 0:0 x0:e->c18:w v1 7'0000100 v1:e->c20:w n3 c20:e->n3:w v2 7'0010100 v2:e->c21:w n6 c21:e->n6:w v3 7'0000110 v3:e->c22:w c25 A B S $b:2 $mux Y c22:e->c25:w c24 A B S $b:1 $mux Y c24:e->c15:w v5 7'0000000 v5:e->c25:w c25:e->c24:w x4:e->c25:w v6 7'x c26 A B S $b:1 $mux Y v6:e->c26:w v7 7'0101100 v7:e->c26:w c26:e->c24:w n3:e->x0:w n3:e->c26:w n6:e->x0:w n6:e->c24:w \n