This variant uses mixed myIRL and cythonized myhdl code segments. Note that the procedural generation is quite a bit faster.
import sys
sys.path.insert(0, "../..")
We import the barrelshifter library:
from library.barrelshifter import *
Compiling /tmp/_cython_inline_08cfa26591b7492f5757aa87dc70c928c0d51984.pyx because it changed. [1/1] Cythonizing /tmp/_cython_inline_08cfa26591b7492f5757aa87dc70c928c0d51984.pyx
Then we create a barrel shifter generator with data width 32 (power 5):
W_POWER = 5
TEST_VALUES = [
(0xdead, 8, 0xdead << 8),
(0x8f01, 15, 0x8f01 << 15),
]
b = BarrelShifterGenerator(W_POWER)
DEBUG CALLING CYTHONIZED CODE
Then we instance it first time in the test bench below. Note the instancing time on this first run.
from myirl.test.common_test import gen_osc
from myirl.emulation.myhdl import *
@block
def top_bs(b):
clk = myirl.ClkSignal()
ce = Signal(bool())
val, result = [ Signal(intbv(0xaa00)[2 ** W_POWER:]) for i in range(2) ]
s = Signal(intbv()[W_POWER:])
inst = [
b.barrel_shifter(clk, ce, val, s, result, False),
gen_osc(clk, 2)
]
@instance
def stim():
for item in TEST_VALUES:
ce.next = False
s.next = item[1]
val.next = item[0]
yield(clk.posedge)
ce.next = True
yield(clk.posedge)
yield(clk.posedge)
print(result)
assert result == item[2]
raise StopSimulation
inst += [ stim ]
return inst
@utils.timer
def test(b):
return top_bs(b)
design = test(b)
DEBUG CREATE wrapper module for top_bs (EmulationModule 'top_top_bs') Declare obj 'barrel_shifter' in context '(LIB: BarrelShifterGenerator 'bs')' Declare obj 'shifter_stage' in context '(LIB: BarrelShifterGenerator 'bs')' Declare obj 'cshift' in context '(LIB: BarrelShifterGenerator 'bs')' Module bs: Existing implementation cshift, rename to cshift_1 Module bs: Existing implementation shifter_stage, rename to shifter_stage_1 Module bs: Existing implementation shifter_stage, rename to shifter_stage_2 Module bs: Existing implementation shifter_stage, rename to shifter_stage_3 Module bs: Existing implementation shifter_stage, rename to shifter_stage_4 Creating process '_run/assign' with sensitivity (clk'rising,) Creating sequential 'top_bs/stim' Finished test in 0.2160 secs
Running the test bench again, the duration is a little less than on the first run, because this module was already compiled.
design = test(b)
Finished test in 0.0139 secs
Finally, the quick & dirty verification:
from myirl import targets
from myirl.test.common_test import run_ghdl
f = design.elab(targets.VHDL, elab_all = True)
f += b.elab(targets.VHDL)
# print(f)
run_ghdl(f, design, vcdfile = 'bs.vcd', debug = True)
Elaborating component top_bs__BarrelShifterGenerator Writing 'top_bs' to file /tmp/myirl_top_top_bs_dzf9st8l/top_bs.vhdl Creating library file /tmp/myirl_module_defs_kmyuipw3/module_defs.vhdl Elaborating component shifter_stage__BarrelShifterGenerator_s32_s32_s1_16_s1_0_0 Writing 'shifter_stage_4' to file /tmp/myirl_bs_gv9ug3vk/shifter_stage_4.vhdl Elaborating component shifter_stage__BarrelShifterGenerator_s32_s32_s1_8_s1_0_0 Writing 'shifter_stage_3' to file /tmp/myirl_bs_gv9ug3vk/shifter_stage_3.vhdl Elaborating component shifter_stage__BarrelShifterGenerator_s32_s32_s1_4_s1_0_0 Writing 'shifter_stage_2' to file /tmp/myirl_bs_gv9ug3vk/shifter_stage_2.vhdl Elaborating component shifter_stage__BarrelShifterGenerator_s32_s32_s1_2_s1_0_0 Writing 'shifter_stage_1' to file /tmp/myirl_bs_gv9ug3vk/shifter_stage_1.vhdl Elaborating component cshift__BarrelShifterGenerator_s1_s1_s1_s1_s1_0_0_1 Writing 'cshift_1' to file /tmp/myirl_bs_gv9ug3vk/cshift_1.vhdl Elaborating component cshift__BarrelShifterGenerator_s1_s1_s1_s1_s1_0_0_0 Writing 'cshift' to file /tmp/myirl_bs_gv9ug3vk/cshift.vhdl Elaborating component shifter_stage__BarrelShifterGenerator_s32_s32_s1_1_s1_0_0 Writing 'shifter_stage' to file /tmp/myirl_bs_gv9ug3vk/shifter_stage.vhdl Elaborating component barrel_shifter__BarrelShifterGenerator_s1_s1_s32_s5_s32_0 Writing 'barrel_shifter' to file /tmp/myirl_bs_gv9ug3vk/barrel_shifter.vhdl Creating library file /tmp/myirl_module_defs_ou6htrhd/module_defs.vhdl ==== COSIM stdout ==== ==== COSIM stderr ==== /tmp/myirl_module_defs_ou6htrhd/module_defs.vhdl:6:1:warning: package "module_defs" was also defined in file "/tmp/myirl_module_defs_kmyuipw3/module_defs.vhdl" [-Wlibrary] ==== COSIM stdout ==== analyze /home/testing/src/myhdl2/myirl/targets/../test/vhdl/txt_util.vhdl analyze /home/testing/src/myhdl2/myirl/targets/libmyirl.vhdl analyze /tmp/myirl_bs_gv9ug3vk/cshift.vhdl analyze /tmp/myirl_bs_gv9ug3vk/cshift_1.vhdl analyze /tmp/myirl_bs_gv9ug3vk/shifter_stage.vhdl analyze /tmp/myirl_bs_gv9ug3vk/shifter_stage_1.vhdl analyze /tmp/myirl_bs_gv9ug3vk/shifter_stage_2.vhdl analyze /tmp/myirl_bs_gv9ug3vk/shifter_stage_3.vhdl analyze /tmp/myirl_bs_gv9ug3vk/shifter_stage_4.vhdl analyze /tmp/myirl_bs_gv9ug3vk/barrel_shifter.vhdl analyze /tmp/myirl_top_top_bs_dzf9st8l/top_bs.vhdl elaborate top_bs ==== COSIM stderr ==== ==== COSIM stdout ==== 0x00DEAD00 0x47808000 /tmp/myirl_top_top_bs_dzf9st8l/top_bs.vhdl:69:9:@22ns:(assertion failure): Stop Simulation /tmp/top_bs:error: assertion failed in process .top_bs(myirl).stim /tmp/top_bs:error: simulation failed ==== COSIM stderr ====
0
# !cat -n /tmp/barrel_shifter.vhdl
from library.test import *
l = cy_library("gna", targets.VHDL)
DEBUG CALLING CYTHONIZED CODE
def test1():
clk = ClkSignal()
a, b = [ Signal(bool()) for _ in range(2) ]
u = l.unit0(clk, a, b)
test1()
Declare obj 'unit0' in context '(LIB: cy_library 'gna')'
Creating process '_run/worker' with sensitivity (clk'rising,)