Toggle navigation
JUPYTER
FAQ
View on GitHub
Execute on Binder
block_name
branch
GF12LPP_tapeout
add_testcases
adder_test
arch_exploration
binder
block_name
bram_changes
clk_bufmap
compilation_fixes
default_net_type
demo_docs
dependabot/submodules/vtr-verilog-to-routing-7950a1b
dependabot/submodules/yosys-bfe0596
dff_techmap
docker
documentation
explicit_verilog
flow_dev
fpga_spice
ganesh_dev
gg_ci_cd_dev
gg_ci
gg_cleanup
gg_dev_routing_fixes
gg_dev
gg_docs
github-action-optimizations
github-actions-test
hard_logic_bitstream_annotation
hetergeneous_arch
tag
v1.2.0
v1.1.541
v1.1.525
v1.1.0
v0.3-alpha
v0.2-alpha
v0.1-alpha
Final1.1
OpenFPGA
docs
source
manual
fpga_verilog
Name
..
figures
fabric_netlist.rst
index.rst
mock_fpga_wrapper.rst
testbench.rst