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v0.1-alpha
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GF12LPP_tapeout
add_testcases
adder_test
arch_exploration
binder
block_name
bram_changes
clk_bufmap
compilation_fixes
default_net_type
demo_docs
dependabot/submodules/vtr-verilog-to-routing-4d881fa
dependabot/submodules/yosys-df3c62a
dff_techmap
docker
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explicit_verilog
flow_dev
fpga_spice
ganesh_dev
gg_ci_cd_dev
gg_ci
gg_cleanup
gg_dev_routing_fixes
gg_dev
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github-action-optimizations
github-actions-test
hard_logic_bitstream_annotation
hetergeneous_arch
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v1.2.0
v1.1.541
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v1.1.0
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ARCH
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sample_arch.xml